The invention pertains to the field of information processing systems and relates to a particular embodiments of processors that can be used in these systems.
Typically, an information processing system comprises a central subsystem that can communicate with one or more peripheral subsystems. The central subsystem is composed of one or more processors connected, for example by a bus, to a central memory and to one or more input/output units. The input/output units enable communication between the central subsystem and the peripheral subsystem.
The function of each processor is to execute program instructions contained in the central memory. To do this, a processor includes means for addressing the memory, in order to access the instructions and data necessary for processing information. To shorten the mean access time to these instructions and data, the processors are typically provided with a cache memory that serves as a buffer between the central memory and the processing circuits of the processor.
For small systems, in modern very large scale integrated technology or VLSI, the processing circuits of the processor can all be integrated into a single integrated circuit, or chip. For less powerful processors, contrarily, despite the steadily increasing scale of integration, the circuits of the same processor must be distributed among a plurality of integrated circuits. To this end, the processor is subdivided into a plurality of functional units, each of which corresponds to one or more integrated circuits. Thus each integrated circuit of the processor can comprise a specialized processing unit, which contributes to executing the set of machine instructions that the processor can execute. Naturally, each processing unit must be capable of communication with the central memory by way of the cache memory. Moreover, depending on the functional format selected, specific links must be provided that enable communication among these units.
Among the set of processing circuits included in the various units of the processor, distinctions are typically made between a command portion, often called a "command block", and a processing portion, generally called the "data path". The command block drives the addressing circuits and the data path as a function of the instructions received. The addressing circuits command the cache memory to drive both the transfer of the instructions and operands to the processing circuits and the transfer of the results processed by these circuits to the cache memory.
In the case of processors having a large instruction set, the microprogramming technique is generally used for the command block. The command block then essentially comprises a hard-wired microsequencer associated with a microprogram memory. As a function of the operating code of the instruction to be executed and of the logic state of the processor, the microsequencer executes an addressing of the microprogram memory, generally upon each cycle. At its output, the memory furnishes microprogram words that trigger the sending of command signals to the various circuits. Naturally, the command block may also include entirely hard-wired circuits, especially for executing certain functions for which faster optimization is desired.
A typical solution for making the microprogrammed command blocks of a processor is to provide a unit specialized for this function. The command block is then contained entirely within this unit, which may be in the form of an integrated circuit, generally associated with one or more external microprogram memories. European Patent Application Serial No. 85 113207.6, published as No. EP-A-17861 on Apr. 23, 1986, and entitled "Distributed Control Store Architecture", may be mentioned as an example of such a command block.
In this version, each processing unit is commanded in centralized fashion in the command block. As a result, each unit contributes at every moment to the execution of the same microinstruction. It has been seen that the various processing units of the processor are equivalent to sharing the set of processor functions.
For example, a first unit will be assigned the addressing function; another unit will be assigned the logical and digital and decimal arithmetic processing functions; a third unit will be assigned the floating point operations. With this type of functional format, the execution of an instruction, that is, of an associated microprogram, generally does not require the simultaneous effective functioning of these three units. For example, if the instruction comprises adding an operand contained in memory to the contents of a register of the processor and arranging the result in this register, its execution includes the following steps:
1) calculation of the real address of the operand from the logical address defined by the instruction;
2) addressing of the memory, loading the operand into the calculation unit, and execution of the operation;
3) writing the result in the register.
In this example, it can be seen that only the addressing unit is used during step 1, and only the calculation unit is used during steps 2 and 3. Thus when one unit is working the others are inactive, which does not represent optimal utilization of the equipment.